Formal Verification Engineer
An exciting semiconductor startup is seeking an outstanding formal verification
engineer to develop a new type of massively parallel architecture.
This is a rare and exciting opportunity to join an evolving team and company,
allowing you to influence the future of both processor architectures and
database systems.
Job Description
We are looking for highly motivated engineers who love the challenge and the opportunity
of a small company. Join us and be a part of a small and dynamic team, which revolutionizes the parallel processor architecture.
Qualifications
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BSc in Electronics Engineering
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3+ Years of industry experience in formal verification.
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Team Player, with excellent interpersonal skills.
Advantages
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Experience as a verification engineer and knowledge in System Verilog
and UVM methodology. -
Knowledge with Jasper.