System Validation Engineer
Speedata is modernizing analytics infrastructure with the first purpose-built ASIC processor, the Analytics Processing Unit (APU), for analytics and AI data workloads. Delivering up to 100x faster Apache Spark performance while cutting infrastructure TCO by 90%, the APU executes analytics operations directly in silicon with seamless integration and no code changes.
We are looking for a Senior System Validation Engineer to drive system-level debug, root-cause analysis, performance optimization, pre- and post-silicon validation for a complex acceleration SoC platform.
You’ll work across hardware, firmware, and high-level software domains to ensure stable, high-performance operation — from emulation-based pre-silicon verification through silicon bring-up and productization.
Hands-on system engineer experienced in cross-layer debug, performance analysis, and bring-up of complex SoC platforms, spanning hardware, firmware, and high-level software.
Requirements
B.Sc. or M.Sc. in Electrical or Computer Engineering, or related field.
5+ years of experience in SoC or platform-level engineering, focusing on debug, analysis, and integration.
Proven expertise in HW/FW/SW interaction, system-level debugging, and cross-layer analysis.
Strong understanding of compute architectures, memory and interconnect systems, and Linux-based environments.
Hands-on experience with both low-level firmware and higher-level system software.
Excellent analytical, communication, and cross-team collaboration skills.
Preferred
Experience with compute or AI acceleration SoCs.
Familiarity with PCIe and/or DDR subsystems and their performance characteristics.
Experience with emulation platforms or silicon validation environments.
Scripting or automation skills (Python, Bash, etc.) for debug and performance
Key Responsibilities
Lead system-level debug of complex issues spanning ASIC, firmware, and software.
Reproduce, isolate, and root-cause functional, performance, and stability problems.
Participate in pre-silicon system validation on emulation platforms, validating HW/SW interactions and key system flows.
Collaborate across ASIC, firmware, and software teams to drive fixes, design improvements, and long-term reliability.
Characterize system performance, identify bottlenecks, and ensure consistent scalability across workloads.
Partner with software and engineering teams to define and improve debug infrastructure and methodologies.
Drive system integration and bring-up of new silicon and platforms, enabling core system functionality.